Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the device size decreases.
In some integrated circuit designs there has been a desire to eliminate the use of polysilicon gate electrodes to improve device performance with decreased feature sizes. Replacing polysilicon gate structures with metal gate stacks is one solution. A typical metal gate stack includes a metal gate that overlies a high dielectric constant (high-K) dielectric layer and an interlayer of a dielectric oxide material that is disposed between the high-K dielectric layer and a semiconductor substrate. Unfortunately, the various metal gate stack materials sometimes face significant difficulties that can result in threshold voltage V(t) instability and performance degradation of the devices. These problems are related to the high amount of bulk defects and interface states (e.g., interface traps in the bulk of the interlayer or high-K dielectric layer due to the existence of dangling bonds, e.g., partial or imperfect bonds between adjacent atoms resulting in free electrons around the atoms) in the metal gate stack, leading to negative bias temperature instability (NBTI) and positive bias temperature instabilities (PBTI) issues.
Accordingly, it is desirable to provide integrated circuits and methods of forming integrated circuits that reduce the number of interface and bulk defects in a metal gate stack to improve, for example, NBTI and PBTI behavior. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.